1. Field of the Invention
This invention relates generally to programmable logic devices, and more particularly to programmable logic devices having buried state registers.
2. Description of the Related Art
Programmable logic devices such as the programmable array logic (PAL) device offer digital designers a flexible and cost effective implementation for complex logic circuits. PAL, the acronym for a Programmable Array Logic device is a registered trademark of Monolithic Memory, Inc. A typical PAL includes a fuse programmable array of AND gates, and a fixed array of OR gates. In some PALs, the outputs of the OR gates are coupled directly to an I/0 pin, and in other PALs the outputs of the OR gates are input into clockable, D-type or S/R-type registers.
PALs having clockable registers are ideal for use as state machines or, as they are sometimes called, sequencers. A state machine includes a number of registers which store the current state of the machine, input combinatorial logic, and output combinatorial logic. Typically, the outputs of the input combinatorial logic determine the next state to be stored within the state registers, and the current state stored in the state registers form a part of the input to the output combinatorial logic. Quite frequently, outputs of the output combinatorial logic are fed back as inputs to the input combinatorial logic.
Complex state machine designs push the limits of prior art PAL devices. For a variety of practical technical and economic reasons, it is desirable to keep the PAL device package as small as possible and to limit the number of pins associated with the package PAL device designers found that one way to shrink package size is to provide several "buried" state registers which can be used to store the current state number, and separate output registers which can output data to an I/0 pin. By not assigning a I/0 pin to the buried state registers the number of pins required to implement the device is reduced.
A problem with the above mentioned prior art PAL design having separate buried state registers and output registers is that it is difficult to observe the contents of the buried state registers. With such designs, the output of a buried state register must be clocked through the output combinatorial logic and an output register before appearing at an I/0 pin. This process can take several cycles, and is thus both inconvenient and time consuming.
Another problem with the above mentioned prior art PAL design is that it is difficult to preload the buried and output registers for debugging purposes. Without a preloading capability, a sequence of inputs to the device would have to be devised to attain a desired state within the PAL, which again is an inconvenient and time consuming process.